Abstracts for Costas J. Spanos

The EECS Research Summary for 2003


Manufacturing Issues in Extreme Ultraviolet Lithography

Jason Cain
(Professor Costas J. Spanos)

As feature sizes in modern integrated circuits continue to decrease below 100 nm, the physics of conventional deep ultraviolet (DUV) optical lithography impose severe limitations. Past efforts to improve the resolution of lithography systems have been based upon reducing the wavelength of the light source. Current state-of-the-art lithography systems use a source wavelength of 193 nm. However, decreasing the wavelength below this level is problematic because at shorter wavelengths most materials become absorptive. Although much research has been done to develop 157 nm lithography tools, this has proven to be costly and difficult, and progress has been slower than expected.

Therefore, it seems that a "quantum leap" is needed in order to keep up with the relentless progress of Moore's Law. Extreme ultraviolet (EUV) lithography at a wavelength of about 13.5 nm has been proposed as a potential replacement for DUV lithography. In order to minimize problems with absorption, EUV lithography tools rely on reflective optics made of silicon/molybdenum multilayer mirrors instead of the refractive optics found in DUV systems. Early results have been encouraging [1], and this is now an area of active research.

A system for performing static lithographic exposures has been constructed at the Advanced Light Source at the Lawrence Berkeley National Laboratory [2]. This system is currently being used to characterize new high numerical aperture optics and to explore issues related to the future manufacturing possibilities for EUV lithography. These issues include photoresist development, mask fabrication and defect problems, and improved modeling of the EUV exposure process. We wil be exploring these issues with emphasis on control and metrology to characterize and improve the EUV lithography process.

[1]
D. A. Tichenor et al., "Performance Upgrades in the EUV Engineering Test Stand," Emerging Lithographic Technologies, Proc. SPIE, Vol. 4688, 2002.
[2]
P. P. Naulleau et al., "Static Microfield Printing at the Advanced Light Source with the ETS Set-2 Optic," Emerging Lithographic Technologies, Proc. SPIE, Vol. 4688, 2002.

Send mail to the author : (jcain@eecs.berkeley.edu)

Electrical Impedance Tomography Based Metrology for Semiconductor Manufacturing*

Michiel Kruger
(Professor Costas J. Spanos)
UC-SMART

In this research project we investigate the feasibility of a class of sensors for semiconductor manufacturing applications. The variables that these sensors can measure include etch rate, temperature, and plasma induced potentials.

The common theme shared by this class of sensors is that they are based on electrical impedance tomography (EIT). EIT involves injecting currents into an object while measuring the induced potentials on the surface of the object. The internal conductivity distribution can be approximately deduced from these measurements. This estimation problem is in general non-linear and poorly conditioned. Simulations have been performed to assess the potential performance of EIT based sensors in semiconductor manufacturing.

In a semiconductor manufacturing context, chemical and physical effects can induce conductivity changes in the interior of the wafer being processed. By placing electrodes at the wafer periphery and measuring potentials across these electrodes, we can infer conductivity changes. This can, in turn, be related to physical and chemical effects through process models. We have built a prototype etch-rate sensor based on this technology and it is being tested in the UC Berkeley Microfabrication Laboratory. The figure below shows the estimated change in thickness after wet etch using EIT (left) and the optically measured change in thickness (right).


Figure 1: Estimated change in thickness using EIT (left) and optically measured change in thickness (right)

Send mail to the author : (kruger@jagger.me.berkeley.edu)

Proposed Framework for Lithography Process Control Using Prolith and Full-Profile Metrology*

Paul Friedberg
(Professor Costas J. Spanos)
Small Feature Reproducibility Program

In DUV photolithography, mask patterns and processes are increasing in complexity, while IC critical dimensions continue to shrink at a rapid pace. As a result, the proportional variability of the process will increase to unacceptable levels unless a means of more advanced process control is introduced. Previously standard offline pilot-lot experiments now prove to be too costly and difficult. One attractive and potentially highly viable alternative is simulation-based advanced process control. [1,2] The proposed control framework exploits scatterometry, which provides in-situ, full-profile metrology [3]. The major obstacle to implementing scatterometry in a process control setting is profile inversion—deriving estimated input conditions from the measured profile. In this work, a first-principle-based process simulator (Prolith [4]) is used to simulate the lithography process and create a library of profile-to-input-conditions pairs. These profiles are then used to generate simulated diffraction responses, resulting in a library of diffraction-responses-to-input-conditions pairs. Finally, the empirically measured diffraction response will be matched to a simulated diffraction response in this library, whose accompanying set of input conditions should estimate the actual input conditions well. Preliminary, simulation-only results suggest that the framework has the potential to be successful, particularly if approximate values of the input conditions are provided during the matching step. However, it is expected that the success of the framework in reality will hinge on how well Prolith models the actual lithography process, the levels of measurement noise, and the method of constructing the simulated library. The current focus of effort in this research is determining how to build a library with balanced sensitivity across all input parameters, as well as diagnosing the empirical performance of the framework.

[1]
C. Gould, “Advanced Process Control: Basic Functionality Requirements for Lithography,” SPIE, Vol. 4434, 2001.
[2]
A. Zeidler, K. Veenstra, and T. Zavecz, “Advanced Statistical Process Control: Coltrolling Sum-0.18 µm Lithography and Other Processes,” SPIE, Vol. 4434, 2001.
[3]
X. Niu, N. Jakatdar, J. Bao, C. J. Spanos, and S. Yedur, “Specular Spectroscopic Scatterometry in DUV Lithography,” SPIE, Vol. 3677, 1999.
[4]
C. Mack, “PROLITH: A Comprehensive Optical Lithography Model,” SPIE, Vol. 538, 1985.

Send mail to the author : (pfriedbe@eecs.berkeley.edu)

Integrated CMP Metrology and Modeling with Respect to Circuit Performance

Runzi Chang
(Professor Costas J. Spanos)
(UC-SMART) SM97-01

As the scaling efforts and complexity of circuit design continue to grow, interconnect variation becomes one of the limiting factors of circuit performance [1]. The systematic nature of the pattern-density dependency in chemical mechanical polishing (CMP) makes previously used approaches to statistical circuit analysis, such as worst-case analysis, insufficient and inaccurate. In this project, we will build models for the oxide and copper CMP process so that the systematic components of the interconnect variation can be decomposed from the total variability. The reduced randomness will enable more aggressive circuit (interconnect) design.

This project has two phases: during the first phase we will use library-based scatterometry as a novel metrology tool to monitor the oxide profile evolution [2,3]. Subsequently, we will use the profiles to build models for oxide CMP. During the second phase, based on the knowledge of oxide polishing processes, we will design test structures, perform characterization experiments, and develop physical or semi-empirical models for copper dishing and oxide erosion in the damascene process [4]. We also plan to integrate the CMP variation model into a circuit performance simulation tool, and study the effects of CMP variation on circuit performance. A long term objective of this project is to provide designers with the tools that will allow design optimization while properly accounting for CMP variability.

[1]
C. J. Spanos, Z. Lin, L. S. Milor, and Y. T. Lin, "Circuit Sensitivity to Interconnect Variation," IEEE Trans. Semiconductor Manufacturing, Vol. 11, No. 4, November 1998.
[2]
R. Chang, "Full Profile Oxide CMP Metrology," master's thesis, UC Berkeley, May 2001.
[3]
R. Chang and C. J. Spanos, "Full Profile Inter-Layer Dielectric CMP Analysis," Proc. IEEE Int. Symp. Semiconductor Manufacturing, October 2001.
[4]
J. Luo, D. Dornfeld, and R. Chang, "A Time Dependency CMP Model of Dishing and Erosion in Copper Damascene Process based on Linear Viscoelasticity," Chemical Mechanical Planarization Int. Conf., October 2002.

More information (http://andros.eecs.berkeley.edu/~rchang) or

Send mail to the author : (rchang@eecs.berkeley.edu)