Transistor scaling below 50 nm gate lengths will likely require the incorporation of new device structures in order to adequately control short-channel effects. A promising candidate is the FinFET, a double-gate MOSFET structure [1,2]. The device consists of self-aligned double gates surrounding a thin silicon slab (the “fin”), which can sufficiently suppress short-channel effects.
Thus far, device fabrication has taken place in a research environment and can consequently make use of non-standard tools such as electron beam lithography. In this work, a manufacturable FinFET process is developed using standard processing tools found in an industrial fabrication facility. Critical process steps have been evaluated using short-loop experiments, and initial device results have been obtained. Working transistors down to 10 nm in gate length have been successfully fabricated. Continued work will focus on achieving appropriate threshold voltages in order to study circuit performance.
Semiconductor memories such as DRAM play an increasingly important part in determining the performance of microelectronic products. Their role has raised the demand for reliable, high density memories with fast data access and low power consumption. However, significant challenges must be overcome in scaling DRAM. Reducing the transistor's off-state leakage, for example, can require high substrate doping to sustain a large threshold voltage. Unfortunately, this approach enhances trap-assisted tunneling and leads to tail bits with small retention times. Another problem is the integration of a small storage capacitor in a technology which should provide an adequate sensing signal margin, long retention time, and soft error protection. As a result, it is unclear if DRAM can scale below feature sizes of 100 nm without changes in the standard 1 transistor/1 capacitor (1T/1C) cell design.
In this study, we investigate three new approaches at scaling DRAM. First, double-gate DRAM (DG-DRAM) is a new memory technology which embodies a thin body, double-gate structure. Scalability is intrinsic to its unique, compact design. We have compared DG-DRAM against other capacitorless DRAM technologies, considered variations in its cell design, performed experimental and simulation measurements, and explored soft error problems. In addition, two other capacitorless memory concepts are investigated. These include an improved version of a direct tunneling floating gate device, featuring a large threshold voltage window and superior data retention. A new direct tunneling, trap-based memory technology is also developed using conventional CMOS materials. These ideas represent novel and manufacturable approaches at bridging the gap between current CMOS memories and future technologies.
Controllability of off-state leakage current, with retention of large on-state drive current, is the primary challenge for scaling complementary metal oxide semiconductor (CMOS) transistor gate lengths into the nanoscale regime. Fully depleted ultra-thin-body (UTB) SOI metal oxide semiconductor field effect transistor (MOSFET) structures provide excellent suppression of short channel effects and performance improvement, and hence are promising for sub-70 nm CMOS technology . In order to avoid mobility degradation and threshold-voltage (VT) variation due to channel dopant fluctuations, it is desirable to use an undoped or very lightly doped (<1017 cm-3) silicon body. In this case, VT adjustment must be achieved by gate work function engineering, in the range from 4.4-5.0 V for a fully depleted SOI CMOS technology . Ideally, the technique for adjusting the gate work function should not utilize common dopants in Si, in order to avoid problems due to dopant penetration through ultra-thin gate dielectrics during the source/drain (S/D) annealing step(s). These requirements essentially rule out polycrystalline silicon (poly-Si) as a candidate gate material for nanoscale UTB SOI CMOSFETs. For simplicity of process integration, it is preferable to deposit a single gate material and subsequently adjust its work function selectively (e.g., in the n-channel vs. p-channel regions) as required. Molybdenum (Mo) is applied as the gate material to achieve the proper VT (-0.2 V) in p-channel UTB SOI MOSFETs for the first time, and VT adjustment via nitrogen implantation is demonstrated. Continued work will focus on investigating the statistical variation of the threshold voltage due to the nitrogen implantation and achieving appropriate threshold voltages with high-K dielectric (HfO2).
The main barrier to full exploitation of SOI/CMOS performance and power is that the design and fabrication of a dedicated chip is a risky process because present tools are neither accurate enough nor efficient enough for fast turnaround and high probability of first-pass success. In this project we address the model accuracy issue. A critical element of all integrated system designs is the SPICE model. SPICE modeling is the standard approach for precise design of critical-path subcircuits in all large systems, as well as the basis for computing the look-up tables used for higher-level timing simulation. Recent versions of the BSIM3 model, based on the physics of short channel MOSFETs, very accurately represent the behavior of the current generation of bulk silicon devices at frequencies up to around 1 GHz. However, current models are inadequate for frequencies much above that, because the intrinsic input resistance and substrate resistance are ignored. Furthermore, the best widely available SOI model, BSIMSOI, does not represent floating body behavior accurately enough to simulate correct output characteristics of fully depleted (FD)SOI devices even at DC, and little is known of the SOI body charging effect at >1 GHz. We will develop an improved FDSOI model based on the existing BSIMSOI model. FDSOI transistors will be fabricated at MIT's Lincoln Laboratory with gate lengths of 180 nm and up, and they will be characterized by both DC and S-parameter measurements at frequencies up to 50 GHz. A new model which includes intrinsic input resistance and SOI floating body effects will be developed at UC Berkeley. The effort will focus initially on DC behavior and then move to representation of RF effects at a frequency of at least 10 GHz.
1Staff, MIT Lincoln Lab
2Visiting Professor, Hong Kong University of Science and Technology
Scaling and high performance advantages make SOI an important CMOS technology. However, the main barrier to full exploitation of SOI performance and power is that the design of an SOI chip is a relatively risky process because the relative lack of design experience makes it difficult to achieve fast turnaround and high probability of first-pass success. To surmount this barrier, a robust and physically accurate SPICE (compact) model is needed. SPICE modeling is the standard approach for precise design of critical-path sub-circuits in all large systems, as well as the basis for computing the look-up tables used in higher-level timing simulators. Cell libraries and IP blocks are in turn designed using the speedier simulations. A compact SOI MOSFET model is crucial to SOI circuit design. The goal of this work, therefore, is to establish a standard SOI model for the semiconductor industry.
1Visiting Professor, Hong Kong University of Science and Technology
As the microelectronics industry is fast approaching the limit of bulk CMOS scaling, there are extensive research activities on double-gate MOSFETs which can potentially further extend CMOS scaling to 10 nm gate dimensions. The topology of the double-gate device is fundamentally different from that of a bulk or SOI device in that the second gate can be either tied together with the first gate or biased separately. The implications of the additional feature on circuit performance need to be understood and evaluated at the circuit level with a sound compact model. As a result, there is a strong demand on a compact model that can be implemented into the existing circuit simulation infrastructure.
The goal of this project is to develop a generic non-structural dependent compact model for double-gate CMOS, implemented in the BSIM framework. The model will be physics-based and general enough to cover various structures of double-gate MOSFETs. The model will also account for arbitrary work functions and separately controlled gates. From a circuit application perspective, the compact model will be widely applicable to different biasing schemes, e.g., both gates switching or separately biased (DC or AC). The ultimate objective is to provide a predictive yet versatile tool for circuit designers to evaluate the performance benefits of the general and specific features of a double-gate MOSFET technology, thus giving a guideline to the selection of double-gate structures.
1Visiting Professor, Hong Kong University of Science & Technology