Abstracts for Ali Niknejad

The EECS Research Summary for 2003


SPICE Model Development for FDSOI MOSFETs above 10 GHz

Hui Wan, Pin Su, Peter W. Wyatt1, and Mansun Chan2
(Professors Chenming Hu and Ali Niknejad)
MIT Lincoln Lab

The main barrier to full exploitation of SOI/CMOS performance and power is that the design and fabrication of a dedicated chip is a risky process because present tools are neither accurate enough nor efficient enough for fast turnaround and high probability of first-pass success. In this project we address the model accuracy issue. A critical element of all integrated system designs is the SPICE model. SPICE modeling is the standard approach for precise design of critical-path subcircuits in all large systems, as well as the basis for computing the look-up tables used for higher-level timing simulation. Recent versions of the BSIM3 model, based on the physics of short channel MOSFETs, very accurately represent the behavior of the current generation of bulk silicon devices at frequencies up to around 1 GHz. However, current models are inadequate for frequencies much above that, because the intrinsic input resistance and substrate resistance are ignored. Furthermore, the best widely available SOI model, BSIMSOI, does not represent floating body behavior accurately enough to simulate correct output characteristics of fully depleted (FD)SOI devices even at DC, and little is known of the SOI body charging effect at >1 GHz. We will develop an improved FDSOI model based on the existing BSIMSOI model. FDSOI transistors will be fabricated at MIT's Lincoln Laboratory with gate lengths of 180 nm and up, and they will be characterized by both DC and S-parameter measurements at frequencies up to 50 GHz. A new model which includes intrinsic input resistance and SOI floating body effects will be developed at UC Berkeley. The effort will focus initially on DC behavior and then move to representation of RF effects at a frequency of at least 10 GHz.

1Staff, MIT Lincoln Lab
2Visiting Professor, Hong Kong University of Science and Technology

More information (http://www-device.eecs.berkeley.edu) or

Send mail to the author : (wanh@eecs.berkeley.edu)

A Standard Model for SOI Circuit Design

Pin Su, Hui Wan, and Mansun Chan1
(Professors Chenming Hu and Ali Niknejad)
(SRC) 2000-NJ-795

Scaling and high performance advantages make SOI an important CMOS technology. However, the main barrier to full exploitation of SOI performance and power is that the design of an SOI chip is a relatively risky process because the relative lack of design experience makes it difficult to achieve fast turnaround and high probability of first-pass success. To surmount this barrier, a robust and physically accurate SPICE (compact) model is needed. SPICE modeling is the standard approach for precise design of critical-path sub-circuits in all large systems, as well as the basis for computing the look-up tables used in higher-level timing simulators. Cell libraries and IP blocks are in turn designed using the speedier simulations. A compact SOI MOSFET model is crucial to SOI circuit design. The goal of this work, therefore, is to establish a standard SOI model for the semiconductor industry.

1Visiting Professor, Hong Kong University of Science and Technology

More information (http://www.eecs.berkeley.edu/~pinsu) or

Send mail to the author : (pinsu@eecs.berkeley.edu)

Wideband CMOS LC VCOs

Axel Berny
(Professors Robert G. Meyer and Ali Niknejad)

Modern broadband communication systems require highly stable frequency references adjustable over a wide range of frequencies. One such system is a cable tuner, which requires a voltage-controlled oscillator (VCO) capable of tuning between 1.2 and 2.1 GHz and a phase noise below –85 dBc/Hz at a 10 kHz offset from the carrier [1]. Solutions addressing such specifications have traditionally relied on expensive high-end technologies and external components [2]. Today’s CMOS technologies are cost-effective and provide sufficient bandwidth for many RF communication applications. This research project focuses on the design of wideband low-phase-noise frequency VCOs in CMOS.

Although various types of VCOs can achieve a wide tuning range, LC VCOs are most suitable since they generally exhibit lower phase noise. To achieve a wide tuning range using a single resonator, we propose a VCO tuned using a mixed-signal scheme. Its frequency is digitally adjusted in coarse steps and subsequently fine-tuned to the desired value using a varactor device. An amplitude control scheme is also implemented.

The goal of this research project is to establish a framework for the analysis, design, and optimization of wideband low-phase-noise VCOs. Tradeoffs between different candidate LC VCO topologies and between available devices will be investigated. The effects of varactor nonlinearities on phase noise and tuning range will be analyzed. A set of analytical methods will be provided to aid in predicting these effects and any other quantities relevant to the overall VCO performance. Our proposed LC VCO will be integrated within a frequency synthesizer to demonstrate its practical feasibility.

[1]
B. Taddiken, W. Ezell, E. Mumper, et al., “Broadband Tuner on a Chip for Cable Modem, HDTV, and Legacy Analog Standards,” IEEE Radio Frequency Integrated Circuits Symp., Boston, MA, June 2000.
[2]
N. Scheinberg, R. Michels, V. Fedoroff, D. Stoffman, K. Li, S. Kent, M. Waight, and D. Marz, “A GaAs up Converter Integrated Circuit for a Double Conversion Cable TV 'Set-Top' Tuner,” IEEE J. Solid-State Circuits, Vol. 29, No. 6, June 1994.

Send mail to the author : (axelb@eecs.berkeley.edu)