SIS 1.2
SIS is an interactive system for the synthesis of sequential circuits. The input can be given in state table format or as logical equations; a target technology library is given in genlib format. The output is a netlist of gates in the target technology.
The system includes various capabilities that are controlled interactively by the user. These include state minimization, state assignment, optimization for area and delay using retiming, optimization using standard algebraic and Boolean combinational techniques from MISII, and technology mapping for optimal area and delay. Redundancy removal and 100% testability are provided for combinational and scan-path circuits. Formal verification is available for both combinational and sequential circuits, even for circuits with different state encodings.
New features in SIS-1.2 include a new state minimization program, programs to translate between structural VHDL and BLIF, a timing package for analyzing and optimizing synchronous circuits with complex clocking schemes, a power estimation package, a new BDD package, and updates and improvements to timing optimization.
Documentation Included with the Program:
- Installation Notes, man pages, and Release Notes. Available separately for $5.00.
- E. M. Sentovich, K. J. Singh, L. Lavagno, et al., "SIS: A System for Sequential Circuit Synthesis" (UCB/ERL M92/41, May 1992). Available separately for $5.00
Foreign Distribution: Yes