POLIS 0.1
POLIS is a design system for hardware-software co-specification, co-synthesis, and co-verification of real-time embedded systems. It consists of all the components necessary to take high-level description in ESTEREL, Graphical FSM (or possibly other formal languages) into prototype-ready C code and design file for Field Programmable Gate Arrays. Design is done in a unified framework so as to prejudice neither hardware nor software implementation. An FSM-based model is maintained throughout and the formal properties of the design are preserved. Design tradeoffs can be made between different hardware-software partitions, hardware and software styles, types of interfacing mechanisms, and scheduling routines to achieve a satisfactory design).
WWW Address: POLIS 1.0 web site
Documentation Included with the program:
- User's Manual. Available separately for $5.00
- Programmer's Manual. Available separately for $5.00
Foreign Distribution: Yes