Photonically Optimized Embedded Microprocessors (POEM)
Vladimir Stojanovic, Krste Asanović, Rajeev Ram1, Milos Popovic2 and Michael Watts3
Defense Advanced Research Projects Agency
The objective of this effort is to develop a monolithically integrated Complimentary Metal-Oxide-Semiconductor (CMOS) and Dynamic Random-Access Memory (DRAM) photonic device technology along with new circuit and architecture techniques to improve DRAM concurrency, cost, bandwidth and power resulting in dramatic increase in embedded-node energy efficiency (and hence performance). The goal is a CMOS photonic core-to-memory-controller network that will enable energy-efficient coherency traffic as well as access to any DRAM chip in the system, preserving the uniform shared memory model with uniform bandwidth and access latency, which greatly simplifies programming of these highly parallel machines. Cores from any socket will access the Memory Controller (MC) on any other socket via a dedicated photonic bus routed through the star coupler. Using energy-efficient power/message guiding, the MC itself can then directly access one of the DRAM chips attached to its memory channel with full channel bandwidth, saving on chip/bank activation energy through smaller pages and on electrical-interconnect chip-traversal energy through on-chip photonic traversal. This power/message guiding in the MC is one of the key concepts of this project, allowing the decoupling of the bandwidth/capacity trade-off inherent in electrical memory channels. Each MC actively guides laser power/modulated messages to any one of the multiple DRAM chips it controls, providing full bandwidth to the active DRAM chip without the significant signal degradation that would occur in an electrical bus, or the additional power penalty of buffer chips required by electrical point-to-point memory channels. By using CMOS photonic links and networks, monolithically integrated on both the processor and DRAM chips, to connect banks on DRAM chips with many core processor memory controllers, we also plan to reduce the area spent on Input-Output in the DRAM chip and the packaging costs associated with electrical impedance matching. The project has three main innovation thrusts: 1. Photonic Device and Process Technology Development: The photonic device design effort focuses on inventing and implementing the photonic device designs that optimally leverage the native DRAM and CMOS processes with minimal to no process changes, while achieving the aggressive target goals. The process technology development thrust focuses on identifying appropriate materials, layers and fabrication procedures that exist in the standard DRAM and CMOS process flows to enable design of high-performance photonic components with minimal to no process changes, as well as evaluate the impact of any suggested process changes on DRAM performance, cost and competitiveness. This thrust also focuses on the impact of photonic integration (like interlayer optical couplers and dense off-chip couplers) on DRAM packaging. 2. Optical Link Design and Opto-Electronic Integration: This thrust focuses on the implementation of photonic Wavelength Division Multiplexed (WDM) network link circuits in tight interaction with photonic device technology, to produce robust, extremely energy-efficient core-to-MC and MC-to-DRAM photonic networks. Both the circuit and device models and the experimental platform will focus on enabling the joint design and co-optimization of photonic devices and back-end electronic circuits. 3. Photonic Network and Electrical System Design: This thrust is developing both the most suitable architecture for the optically interconnected memory system hierarchy (involving the coherency protocols, and MC architecture, through software simulation and hardware emulation of larger systems), as well as implementing these concepts in hardware on a smaller scale, together with WDM photonics, to demonstrate the final system.
Figure 1: POEM concept - collaboration with Micron Technology
2University of Colorado, Boulder