Research Projects

Performance Analysis of Synchronous Models Implementations on Loosely Time-Triggered Architectures

Alberto L. Sangiovanni-Vincentelli

Multiscale Systems Center

Synchronous languages are used in the most popular software and systems modeling environments because of the availability of tools for validation and verification by simulation or model checking. To preserve the validation results, their implementation must be provably correct with respect to the preservation of the semantics properties of interest. An implementation path for synchronous models can easily be defined for time-triggered platforms, at the expense of some inflexibility. A mapping of synchronous models onto a much less restrictive platform, Loosely Time Triggered Architecture (LTTA), that preserves the communication flows has been defined in [1]. The mapping uses intermediate layers with queues and then backpressure communication channels. Its time performance is analyzed using a virtual clock model with several pessimistic assumptions and limitations, including zero bus delays and no control on schedulability. In this work, we propose the use of Real-Time Calculus (RTC) as a general model for the analysis of such systems, leveraging the work in [2] where RTC was used to analyze multimedia systems with processing pipelines. To apply the analysis to the implementation of synchronous models into LTTA, several additions and fixes to the original analysis are needed, including the modeling of forks and merges of communication paths, an improved analysis of the effective service curves and an improved method that avoids a major problem in the analysis in [2], which results in some cases in zero throughput and infinite latency. Also, we adopted a model of LTTA that allows a more accurate representation of actual LTTA software implementations. Experimental results show that our approaches can indeed improve the computation of effective service curves and provide another approach to analyse the performance of LTTA.

[1]
S. Tripakis, C. Pinello, A. Benveniste, A. Sangiovanni-Vincentelli, P. Caspi, and M. Di Natale, "Implementing synchronous models on loosely time-triggered architectures," IEEE Trans. on Computers, vol. 57, no. 10, pp. 1300–1314, 2008.
[2]
A. Bouillard, L. T. X. Phan, and S. Chakraborty, "Lightweight modeling of complex state dependencies in stream-processing systems," Proc. of IEEE Real-Time and Embedded Technology and Applications Sym., pp. 195–204, 2009.