The RISC-V Instruction Set Architecture
Andrew Waterman, Yunsup Lee, David A. Patterson and Krste Asanović
Intel and Microsoft
RISC-V is a new instruction set architecture (ISA) designed to support computer architecture research and education. Our goals in defining RISC-V include: 1) Provide a realistic but open ISA that captures important details of commercial general-purpose ISA designs and that is suitable for hardware implementation; 2) Provide a small but complete base ISA that avoids ``over-architecting'' for a particular microarchitecture style (e.g., microcoded, in-order, decoupled, out-of-order) or implementation technology (e.g., full-custom, ASIC, FPGA), but which allows efficient implementation in any of these; 3) Support both 32-bit and 64-bit address space variants for applications, operating system kernels, and hardware implementations; Support highly-parallel multicore or manycore implementations; 4) Support an efficient dense instruction encoding with variable-length instruction, improving performance and reducing energy and code size. Support the revised 2008 IEEE 754 floating-point standard. 5) Be fully virtualizable. 6) Be simple to subset for educational purposes and to reduce complexity of bringing up new implementations. 7) Support experimentation with new user-level ISA extensions and specialized variants. 8) Support independent experimentation with new supervisor-level ISA designs. Our intent is to provide a long-lived open ISA with significant infrastructure support, including documentation, compiler tool chains, operating system ports, reference SAME simulators, cycle-accurate FAME-7 FPGA simulators, high-performance FPGA computers, efficient ASIC implementations of various target platform designs, configurable processor generators, architecture test suites, and teaching materials. Initial versions of all of these have been developed or are under active development. This material is to be made available under open licenses (either modified BSD or GPL/LGPL).