Research Projects

Ultra-thin-body & BOX Fully-Depleted SOI MOSFET: Carrier Transport and Performance Enhancement Study (SOIStrain)

Nuo Xu, Tsu-Jae King Liu, Olivier Faynot1, Bich-Yen Nguyen2, Francois Andrieu3, Olivier Weber4 and Thiery Poiroux5

IMPACT UC Discovery ele07-10283

Conventional planar bulk MOSFET is difficult to scale down to sub-20nm node, due to the worsening performance variability and short channel effects. Thin body transistors, including Double-Gated FinFETs and Fully Depleted SOI (FD-SOI) MOSFETs are anticipated to be used in future CMOS technology nodes. Strained Silicon technology is widely used today to boost transistor performances. Thus it’s technically important to examine the strain-induced enhancement in these thin-body transistors, and within nanometer channel lengths. In this project, experimental and TCAD Simulation study of Ultra-thin Body and BOX (UTBB) FD-SOI MOSFET carrier transport issues, including strain enhancement, short channel apparent mobility reduction, ON-state injection velocity impacts. Special attentions are paid to the back biasing tunning to reach optimal device performances vs. power efficiency. Relevant publications [1-3]

Figure 1
Figure 1: Fully Depleted SOI MOSFET TEM cross-sectional view

Figure 2
Figure 2: Calculated Electron and Hole Bandstructures (equi-energy contours in momentum space) from FD-SOI structure, and under different strain configurations

Figure 3
Figure 3: Wafer-bending equipment to introduce mechanical strain, experimentally

[1]
N. Xu*, F. Andrieu, J. Jeon, X. Sun, O. Weber, B.-Y. Nguyen, O. Faynot and T.-J. King Liu “Stress-induced Performance Enhancement in Ultra-Thin-Body Fully Depleted SOI MOSFETs: Impacts of Scaling,” IEEE Symposium on VLSI Technology (VLSI 11'), Kyoto, Japan, Tech. Dig. p.162-163, 2011.
[2]
N. Xu*, B. Ho, F. Andrieu, L. Smith, B.-Y. Nguyen, O. Weber, T. Poiroux, O. Faynot, T.-J. King Liu, “Carrier Mobility Enhancement via Strain Engineering in Future Thin-Body MOSFETs,” IEEE Electron Device Letters, 33, pp.318-320, 2012.
[3]
N. Xu*, F. Andrieu, B. Ho, B.-Y. Nguyen, O. Weber, C. Mazure, O. Faynot, T. Poiroux and T.-J. King Liu, “Impact of Back Biasing on Carrier Transport in Ultra-Thin-Body and BOX (UTBB) Fully Depleted SOI MOSFETs,” IEEE Symposium on VLSI Technology (VLSI 12’), Honolulu, HI, Tech. Dig. p.113-114, 2012.

1CEA-LETI Minatec, 38054 Grenoble Cedax 9, France
2Soitec, Austin TX 78746
3CEA-LETI Minatec, 38054 Grenoble Cedax 9, France
4CEA-LETI Minatec, 38054 Grenoble Cedax 9, France
5CEA-LETI Minatec, 38054 Grenoble Cedax 9, France