Micro-Electro-Mechanical Relays for VLSI Applications
*** THIS PROJECT IS NO LONGER ACTIVE ***
Elad Alon, Tsu-Jae King Liu, Matthew Spencer and Hei Kam
Modern digital circuits in CMOS are operating at an optimum threshold voltage where leakage power is balanced against dynamic power. Consequently, changing the threshold voltage of a CMOS technology will actually increase the energy per operation of digital circuits. This pins the supply voltage of future technologies and implies that scaling will have no energy benefit. In order to put more devices on silicon, an alternative technology to CMOS with a sharper subthreshold slope must be found. Mechanical relays present an interesting candidate for this technology because of their infinite sub-threshold slope. However, the large mechanical delay of these devices requires circuit architectures that are significantly different from those used in CMOS in order to leverage their low on-resistance and infinite off-resistance. A test chip to examine the feasibility of these architectures (and of the device design) has been fabricated and data has been gathered on the operation of relay-based memory, static logic, sequential logic and DACs. Future chips will investigate the details of power gating, timing, arithmetic logic and analog-to-digital conversion using relays. This project is pursued in collaboration with circuit designers at MIT and UCLA.
- F. Chen, M. Spencer, R. Nathanael, C. Wang, H. Fariborzi, A. Gupta, H. Kam, V. Pott, J. Jeon, T. King-Liu, D. Markovic, V. Stojanovic, E. Alon, “Demosntration of Integrated Micro-Electro-Mechanical Switch Circuits for VLSI Applications.” IEEE International Solid-State Circuits Conference Technical Digest, Feb. 2010, pp. 150-151.