Calibration of Time-Interleaved SAR A/D converters
Dusan Stepanovic and Borivoje Nikolic
First demonstrations of functional wireless communication systems operating in recently opened 60GHz frequency band use very simple modulation schemes like BPSK. An alluring way to further increase data throughput in these systems is to increase the complexity of the modulation schemes. One of the main obstacles encountered in practical implementations of such systems is the power of baseband analog-to-digital (A/D) converters. The goal of this research is to build a power efficient A/D converter in 2-3GHz sampling frequency range with resolution of 8 effective bits. The recent resurgence of successive approximation (SAR) A/D converters has demonstrated extreme power efficiency. Although the speed of SAR converters is steadily increasing thanks to the faster transistors in new process technologies it is still far away from our target frequency range. An attractive approach to shift the efficiency of SAR converters towards higher sampling rates is to use time-interleaving of multiple channels. For ultimate power efficiency the A/D converters should operate in the thermal noise limited regime. For moderate resolution SAR converters this requires use of sub-fF capacitors, which brings up the issue of matching due to both layout effects and random fluctuations. Therefore, in addition to standard channel mismatch effects, the nonlinearities of individual channels need to be corrected. In this project we propose a novel deterministic calibration algorithm with rapid convergence that unifies the correction of channel timing, gain and offset mismatch effects and nonlinearities of individual SAR converters.
Figure 1: Block Diagram of Time-Interleaved SAR A/D Converter