Design of Flexible High-Throughput, Low-Power LDPC Decoders
Matthew Weiner and Borivoje Nikolic
National Science Foundation
Low density parity check (LDPC) codes have become popular in high-performance wireless systems because of their excellent error correcting performance. LDPC codes are a type of linear block code, which is characterized by its parity check matrix H. The decoding algorithm uses soft information to iteratively decode a received message by passing messages back and forth between variable and check nodes via a routing network. Fixed decoder designs implement the decoding algorithm for a single H matrix, allowing the use of a simple routing scheme. On the other hand, flexible decoders can switch between different H matrices at the cost of a more complicated routing system. This usually limits their maximum performance and minimum power dissipation compared to fixed designs. In this project, we aim to develop a flexible serial-parallel stream architecture suitable for 60GHz baseband applications. Our goal is a throughput of over 1Gb/s for each code rate and a power dissipation below approximately 100mW, which pushes both power and performance specifications previously reported for flexible decoders. This will be achieved by (1) using a pipelined architecture that requires no large memories to store check or variable messages, (2) exploiting the structure of the matrices to increase the number of check nodes available for lower code rates using the same hardware, and (3) shortening the length of the pipeline for lower rate codes.
- "A 47 Gb/s LDPC decoder with improved low error rate performance," in Proc. Symposium on VLSI Circuits, Kyoto, Japan, Jun. 2009, pp. 286–287.