Research Projects

Low Power LO Generation and Distribution for 60GHz Phased Array Transceivers


Cristian Marcu and Ali Niknejad

Robust communication in the 60GHz band requires a phased array transceiver to overcome path loss and to reduce the effect of interferers. A low power 60GHz phase-locked loop (PLL) with wide tuning range, as shown in Fig. 1, is required to generate the local oscillator (LO) signal for up and down-conversion in the transceiver. However, for scalability and flexibility, a baseband phase shifting architecture is desired, requiring the LO signal to be distributed to every element in the phased array over large distances. A general LO distribution network in shown in Fig. 2. However, this distribution must be performed with low loss and also low power consumption per element such that the LO path does not constrain the overall transceiver power consumption. This research focuses on the design and optimization of the entire LO generation and distribution subsystem with the aim of minimizing power consumption without reducing overall transceiver performance. A prototype 4-element transceiver [1] was designed in 65nm CMOS which included a low power 60GHz PLL (29mW) with wide tuning range (12.4%) as well as an optimized LO distribution network based on the structure shown in Fig. 2. Future work will focus on extending the tuning range of the PLL even further to ensure full coverage of the 60GHz band over process and temperature. Furthermore, a general optimization strategy will be developed for multiple LO distribution schemes.

M. Tabesh, J. Chen, C. Marcu, L. Kong, S. Kang, E. Alon, A. Niknejad, "A 65nm CMOS 4-Element Sub-34mW/Element 60GHz Phased-Array Transceiver," IEEE International Solid-State Circuits Conference, Feb. 2011.