Integrated Voltage Conversion for High-Performance Digital ICs
Hanh-Phuc Le, Elad Alon and Seth R. Sanders
Semiconductor Research Corporation
With the rising integration levels used to increase digital processing performance, there is a clear need for multiple independent on-chip supplies in order to support per-IP or block power management. Simply adding multiple off-chip DC-DC converters is not only difficult due to supply impedance concerns, but adds cost to the platform by increasing motherboard size and package complexity. There is therefore strong motivation to integrate voltage conversion on the silicon. To allow for multiple on-chip supply voltages and simplify the board- and package-level power delivery networks, in this project we are exploring a power delivery architecture consisting of many distributed, fully-integrated switching regulators (for efficient conversion of a single external high-voltage supply) combined with parallel linear regulators to control the AC impedance. Since the parallel linear regulator can be designed to spend minimal power in setting the effective supply impedance, the switching regulator can be optimized purely for conversion efficiency, maximizing the overall efficiency of the system. The key challenge associated with realizing such integrated converters is achieving high efficiency at the high power densities required by high-performance digital logic. In typical CMOS processes, on-die capacitors have significantly higher Q and energy density and lower cost than on-die inductors, leading to several recent efforts exploring fully integrated switched-capacitor (SC) DC-DC converters [1, 2]. We expand upon these previous designs by demonstrating a fully integrated step-down SC converter capable of achieving high efficiency (82%) at high power density (0.55W/mm2) while supporting a wide range of output voltage levels. To support multiple output voltages with this converter, we have developed a “standard cell” converter design that partitions the switches and capacitors in a manner that makes it straightforward to alter the converter’s topology (and hence its conversion ratio). In collaboration with AMD, the converter was implemented and tested in a 32nm SOI test-chip. This preliminary converter supports 3 topologies (2:1, 3:2, and 3:1), an output voltage range of ~0.6V to 1.2V, and achieves a maximum efficiency of 82% at an output power density of 0.55W/mm2. The next step in this project is to look for a solution in order to increase the power density with minimal trade-off in efficiency and finally complete an integrated regulator with a close loop regulation.
Figure 1: Fig. 1: Example On-Die Switching Converter and its Peak Optimal Efficiency vs. Power Density.
- Hanh-Phuc Le, Seth Sanders and Elad Alon, '1W/mm2 Integrated Switched-Capacitor (SC) Converter for High-Performance Digital ICs', ISSCC Student Forum Presentation, Feb. 2009.
- Hanh-Phuc Le, Michael Seeman, Seth Sanders, Visvesh Sathe, Samuel Naffziger, Elad Alon, 'A 32nm Fully-Integrated Reconfigurable Switched-Capacitor DC-DC Converter Delivering 0.55 W/mm2 at 81% Efficiency', ISSCC, Feb. 2010.
- Michael Seeman, Vincent W Ng, Hanh-Phuc Le, Mervin Johns, Elad Alon, Seth R Sanders, 'A Comparative Analysis of Switched-Capacitor and Inductor-Based DC-DC Conversion Technologies', COMPEL, June 2010.
More information: http://bwrc.eecs.berkeley.edu/Research/e-eis/int_conv.html