Research Projects

Air Spacer MOSFET technology


Jemin Park and Chenming Hu

In a 20nm-gate MOSFET with oxide spacer, 77% of the gate charge is due to the gate to plug/diffusion capacitances. Reducing these capacitances will be an increasingly important way to improve the device speed and switching energy/power at 20nm and beyond. Compared to an air-spacer inverter, a conventional nitride-spacer inverter has 82% longer delay and 85% larger switching energy (power consumption). Even a pure-oxide-spacer inverter has 41% longer delay and 48% larger switching energy than the air-spacer inverter. High density memories employ the SAC technology that requires the use of nitride spacers. This significantly raises the gate to plug/diffusion capacitance and increases the delay and switching energy by about 60%. A novel air-spacer SAC device can preserve the 35% area benefit of SAC device while reducing the delay and power by over 75% to levels even better than the non-SAC conventional device. It also reduces the bit-line and word-line capacitances. The result is increased DRAM and SRAM speed, reduced power, and reduced chip size. These air spacer technologies are promising key technology for 20nm generation and beyond.

M. Togo, A. Tanabe, A.Furukawa, K.Tokunaga, and T. Hashimoto. : ‘A Gate-side Air-gap Structure (GAS) to Reduce the Parasitic Capacitance in MOSFETs’, Symposium on VLSI Tech. Dig., p. 38, 1996.
TSUPREM4 User Manual, Synopsys, Mountain View, CA.
SENTAURUS User Manual, Synopsys, Mountain View, CA