Electrical Engineering
      and Computer Sciences

Electrical Engineering and Computer Sciences


UC Berkeley


Research Projects

Modeling of double-gate MOSFETs with independent front- and back-gates (BSIM)

Darsen Duane Lu, Sriramkumar Venugopalan, Muhammed Karim, Ali Niknejad and Chenming Hu

Semiconductor Research Corporation 2055.001

The independent double-gate field-effect transistors (IDG-FETs) (Figure 1) allows the tuning of threshold voltage by changing the back-gate voltage. This provides circuit designers with additional flexibility to resolve the tradeoff between circuit speed and power consumption. The industry is seriously considering IDG-FETs such as ETSOI or UT2B or 15nm to reduce power consumption and variability. The goal of this project is to develop a compact model (SPICE model) for IDG-FETs. We have developed the core I-V and C-V model for IDG-FET and verify it with TCAD and experimental data [1]. Real device effects such as mobility degradation, velocity saturation, quantum effects, short channel effects, parasitic resistances and capacitance, impact ionization, leakage current components are incorporated in the model. The model is implemented in Verilog-A and can be used in most commercial circuit simulators.

Figure 1
Figure 1: (a) Bulk FinFET with two independent gates; (b) SOI FinFET with independent gates; (c) Back-gated SOI MOSFET

D. D. Lu, M. V. Dunga, C.-H. Lin, A. M. Niknejad, and C. Hu, "A Multi-Gate MOSFET Compact Model Featuring Independent-Gate Operation," IEDM, 2007.
D. D. Lu, M. V. Dunga, C.-H. Lin, A. M. Niknejad and C. Hu, “A Computationally Efficient Compact Model for Fully-Depleted SOI MOSFETs with Independently Controlled Front- and Back-Gates,” to be published in Solid State Electronics.

More information: http://www-device.eecs.berkeley.edu/~bsim3