Research Projects

Design of LDPC Decoders for Low Error Rate Performance

Zhengya Zhang, Pamela Lee, Lara Dolecek¹, Borivoje Nikolic, Venkat Anantharam and Martin Wainwright

National Science Foundation CCF-0635372, Marvell, Intel, Infineon Technologies and UC MICRO

Low-density parity-check (LDPC) codes have been demonstrated to perform very close to the Shannon limit when decoded iteratively. Sometimes excellent performance is only observed up until a moderate bit error rate (BER); at a lower BER, the error curve often changes its slope, manifesting a so-called error floor. Such error floors are a major factor in limiting the deployment of LDPC codes in high-throughput applications.

We design a parallel-serial architecture to map the decoders of structured LDPC codes to a hardware emulation platform. Experiments in the low BER region provide statistics of the error traces, which are used to investigate the causes of the error floors [1]. Different classes of errors cause error floors. But even with an optimal implementation, the error floors are inevitable due to certain combinatorial structures of the LDPC code, termed absorbing sets [2]. The effect of absorbing sets in determining the error floor level is influenced by implementation. Conventional decoder implementations tend to induce low-weight weak absorbing sets, and, as a result, elevate the error floor. We propose alternative quantization schemes and demonstrate seemingly inferior algorithms that alleviate the effects of weak absorbing sets [3]. Furthermore, we can exploit the structure of absorbing sets with a redesigned message-passing decoder to escape such local minimum states [4]. The investigative approach and ASIC design approach are unified using a Simulink-based design flow. Rapid prototyping allows us to concurrently explore the algorithmic, architectural and implementation spaces in order to optimize the decoder design.

[1]

GEN03-6: Investigation of Error Floors of Structured Low-Density Parity-Check Codes by Hardware Emulation. Zhang, Zhengya; Dolecek, Lara; Nikolic, Borivoje; Anantharam, Venkat; Wainwright, Martin; Global Telecommunications Conference, 2006. GLOBECOM '06. IEEE Nov. 2006 Page(s):1 - 6.

[2]

Analysis of Absorbing Sets for Array-Based LDPC Codes. Dolecek, L.; Zhengya Zhang; Anantharam, V.; Wainwright, M.; Nikolic, B.; Communications, 2007. ICC '07. IEEE International Conference on 24-28 June 2007 Page(s):6261 - 6268.

[3]

Quantization Effects in Low-Density Parity-Check Decoders. Zhengya Zhang; Dolecek, L.; Wainwright, M.; Anantharam, V.; Nikolic, B.; Communications, 2007. ICC '07. IEEE International Conference on 24-28 June 2007 Page(s):6231 - 6237.

[4]

Z. Zhang, L. Dolecek, B. Nikolic, V. Anantharam, and M. J. Wainwright, "Lowering LDPC error floors by postprocessing," Proc. IEEE GLOBECOM, New Orleans, LA, November 2008.

[5]

Error floors in LDPC codes: Fast simulation, bounds and hardware emulation. Lee, P.; Dolecek, L.; Zhengya Zhang; Anantharam, V.; Borivoje; Wainwright, M.J.; Information Theory, 2008. ISIT 2008. IEEE International Symposium on 6-11 July 2008 Page(s):444 - 448,

¹Massachusetts Institute of Technology