Research Projects - Donald O. Pederson Center for Electronics Systems Design (DOP)
Small Projects
- A Theory of Mutations with Applications to Vacuity, Coverage, and Fault Tolerance
Sanjit A. Seshia, Wenchao Li and Orna Kupferman - Parallel Transistor Level Full-Chip Circuit Simulation
He (Vincent) Peng and Ernest S. Kuh - Parallel Transistor Level Full-Chip Circuit Simulation
Ernest Kuh and Vincent Peng - Platform-based Mixed-Signal System Design
Xuening Sun, Chang-Ching Wu, Alberto L. Sangiovanni-Vincentelli, Pierluigi Nuzzo and Alberto Alessandro Angelo Puggelli - Satisfiability Modulo Theories (SMT)
Rhishikesh Shrikant Limaye, Sanjit A. Seshia and Susmit Jha - Verification-Guided Error Resilience (VGER)
Daniel Holcomb, Wenchao Li and Sanjit A. Seshia - Word-Level Verification of Hardware Designs Using Selective Term-Level Abstraction
Sanjit A. Seshia and Bryan Brady
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