Research Projects - Design of Electronic Systems (DES)
Large Projects
- Algorithms and Frameworks for OCR and Content-based Image Retrieval
Jike Chong, Bryan Christopher Catanzaro, Narayanan Sundaram, Fares Hedayati and Kurt Keutzer - Cyber-Physical Systems: ActionWebs
Claire Tomlin, Edward A. Lee, S. Shankar Sastry, David E. Culler and Hamsa Balakrishnan - Optimizing Semantics-Preserving Implementation of Synchronous Reactive Communication
Guoqiang Wang, Marco Di Natale and Alberto L. Sangiovanni-Vincentelli - Prof. Roychowdhury's Research
Jaijeet Roychowdhury - Ptolemy Project
Edward A. Lee, Hugo Andrade, Christopher Brooks, Dai Bui, Yasemin Demir, John Eidson, Shanna-Shaye Forbes, Jeff C. Jensen, Elizabeth Latronico, Man-Kit Leung, Ben Lickly, Isaac Liu, Slobodan Matic, Eleftherios Matsikoudis, Mary Stewart, Charles Shelton, Stavros Tripakis and Jia Zou - UCLID: Reasoning about Computer Systems with Boolean Methods (UCLID)
Sanjit A. Seshia, Bryan Brady, Susmit Jha and Rhishikesh Shrikant Limaye
Small Projects
- A System-Level Design Methodology for Fault Tolerant Automotive Systems
Mark Lee McKelvin Jr and Alberto L. Sangiovanni-Vincentelli - A Theory of Mutations with Applications to Vacuity, Coverage, and Fault Tolerance
Sanjit A. Seshia, Wenchao Li and Orna Kupferman - Application of Machine Learning Techniques to Improve Convergence Properties of Model-Based OPC Algorithms
Allan Xiao Yu Gu, Peiran Gao and Avideh Zakhor - Automatic Clock Gate Synthesis
Aaron P. Hurst, Robert K. Brayton and Andreas Kuehlmann - Efficient Task Allocation and Scheduling of Concurrent Applications to Multiprocessor Systems
Kaushik Ravindran, Nadathur Rajagopalan Satish and Kurt Keutzer - Functional Symmetries and Their Uses in Optimization and Verification
Donald Chai and Andreas Kuehlmann - Game-Theoretic Timing Analysis
Sanjit A. Seshia - Hardware Implementation of Lossless Compression for Direct-Write Maskless Lithography Systems
Hsin-I Liu, Avideh Zakhor and Borivoje Nikolic - Hierarchy of Finite Simulations of Lazy Linear Hybrid Automata
Susmit Jha, Sanjit A. Seshia and Bryan Brady - Information Flow Security
Susmit Jha and Sanjit A. Seshia - Interfaces for Component-Based Design
Stavros Tripakis, Ben Lickly, Edward A. Lee and Thomas A. Henzinger - Leveraging Task and Data Level Parallelism in Multi-Core Processors
Nadathur Rajagopalan Satish and Kurt Keutzer - Modular Code Generation
Edward A. Lee, Dai Bui and Stavros Tripakis - MOSFET Stress Modeling Using Pattern Functions
Andrew R. Neureuther, Tsu-Jae King Liu, Nuo Xu and Lynn Tao-Ning Wang - Multiprocessor Implementation of Image Recognition
Narayanan Sundaram, Bryan Christopher Catanzaro, Jike Chong and Kurt Keutzer - Parallel Transistor Level Full-Chip Circuit Simulation
He (Vincent) Peng and Ernest S. Kuh - Parallel Transistor Level Full-Chip Circuit Simulation
Ernest Kuh and Vincent Peng - Partition Algorithms for Parallelizing Post-Layout Timing Optimization (PAPPTO)
Bor-Yiing Su, Kurt Keutzer and Christopher Batten - Platform-based Mixed-Signal System Design
Xuening Sun, Chang-Ching Wu, Alberto L. Sangiovanni-Vincentelli, Pierluigi Nuzzo and Alberto Alessandro Angelo Puggelli - Post Decomposition Assessment of Double Patterning Layout
Juliet Alison Rubinstein and Andrew R. Neureuther - Precision Timed Machines (PRET)
Isaac Liu, Ben Lickly, Shanna-Shaye Forbes, Hiren D. Patel and Edward A. Lee - PTIDES: Programming Temporally Integrated Distributed Embedded Systems
Slobodan Matic, Jia Zou, Edward A. Lee, Shanna-Shaye Forbes, Isaac Liu, Jeff C. Jensen and John Eidson - QF_IDL: A Core Optimization Problem in Automated System Design
Matthew Walter Moskewicz and Kurt Keutzer - Qualitative Dynamics of Chua's Circuit
Bharathwaj Muthuswamy and Leon O. Chua - Satisfiability Modulo Theories (SMT)
Rhishikesh Shrikant Limaye, Sanjit A. Seshia and Susmit Jha - Scalability of On-Chip Transmission Lines
Ling Zhang, Chung-Kuan Cheng and Ernest S. Kuh - Scheduling Applications with Variable Task Execution Times onto Heterogeneous Multiprocessors
Nadathur Rajagopalan Satish and Kurt Keutzer - Stimulus Generation for Constrained Biased Random Simulation
Nathan Kitchen, Tobias Welp and Andreas Kuehlmann - Verification-Guided Error Resilience (VGER)
Daniel Holcomb, Wenchao Li and Sanjit A. Seshia - Word-Level Verification of Hardware Designs Using Selective Term-Level Abstraction
Sanjit A. Seshia and Bryan Brady - Zero-Footprint Optical Metrology Wafer
John Gerling and Nathan W. Cheung
Send requests for updates to researchupdates@eecs, or Login to make changes yourself.