Steep-Subthreshold-Slope Transistors for Electronics with Extremely-Low Power (STEEP)
Eli Yablonovitch, Chenming Hu, Tsu-Jae King Liu, Sayeef Salahuddin, Ali Javey, Sapan Agarwal and Sung Hwan Kim
Defense Advanced Research Projects Agency
The Steep-subthreshold-slope Transistors for Electronics with Extremely-low Power (STEEP) program’s goal is to develop novel transistor technologies for logic circuits with extremely low power consumption, without sacrificing performance.
Due to leakage power issues, advanced silicon CMOS transistor technologies will not be suitable for realizing ultra low-power electronics in power-constrained military systems or high-performance computing applications. As a result, it is essential to develop a revolutionary transistor technology that can be operated at much lower bias voltages while still maintaining high performance for logic applications.
The goal of the STEEP program is to develop transistors with very steep-subthreshold-slopes (1/S < 60 mV/dec) at low bias voltages (< 1V) and to establish a high-yield fabrication process in order to realize complex ultra-low power digital circuits. The technical approach will be based on developing band-to-band tunneling transistors operated at low bias voltages with high saturation current and low leakage current. In addition, associated transistor models will also be developed to enable novel ultra-low power circuit designs. At the end of the program, complex demonstration circuits will be able to achieve significant power savings, both active and standby, of at least a factor of 25.
The objective of the STEEP program is to develop revolutionary transistor technologies which achieve subthreshold slope down to 20 mV/decade while maintaining excellent current drive characteristics. STEEP transistors will utilize the mechanism of gate controlled modulation of the energy band alignment between the conduction and valence bands. The key technical challenges of the program include achieving steep-subthreshold-slopes over many decades of current; developing a CMOS compatible fabrication flow; developing novel circuit designs accommodating asymmetric source-drain regions; demonstrating abrupt doping profiles at tunneling junctions; and integrating SiGe, Ge, or compound semiconductors in transistor structures to facilitate the required tunneling currents.
Phase I of STEEP will concentrate on developing band-to-band tunneling transistors with steep-subthreshold-slope and useful drive current at low bias voltage. Phase II will optimize the transistors further reducing the subthreshold slope and bias voltage. In addition, a ring oscillator and a small SRAM circuit will be used to demonstrate the ultra-low-power operation. Phase III will emphasize the development of a high-yield fabrication process with the demonstration of a fully functional large SRAM in an 8 inch wafer technology.
This complex demonstration circuit will make use of such ultra-low power transistors and demonstrate significant power savings. The STEEP transistor technology could enable ultra-low-power digital electronics for revolutionary military capab1ilities in areas such as unattended sensors with unlimited lifetimes or autonomous unmanned air vehicles navigated using vision.