Multi-Gb/s 60GHz Wireless Transceiver Design for Mobile Applications
Chintan Thakkar, Ali Niknejad and Elad Alon
In order to demonstrate techniques suitable for high data rate communication in mobile handsets, we have recently developed a 60GHz transceiver with integrated baseband circuitry in collaboration with other researchers at BWRC . In contrast to OFDM-based transceivers for set-top boxes, our design is inspired by low-power high-speed chip-to-chip serial links. These links have shown that for high bandwidths and relatively low dynamic range (implying simple modulation), analog processing and a minimal number of comparators is significantly more efficient than multi-bit ADC/DSP-based solutions.
Our first transceiver design included a 6-bit digitally programmable analog phase rotator and a 5-tap mixed signal decision feedback equalizer (DFE) to validate the high-speed link-based approach. However, even directional communication at 60 GHz can contain significant multi-path energy beyond 10 taps at rates of 5 GS/s. Due to their power consumption increasing quadratically with the number of taps, extending a purely mixed-signal DFE to a large number of taps would be inefficient. We are therefore exploring a hybrid DFE design consisting of a digital FIR filter and DAC combined with mixed-signal taps. The mixed-signal taps relax the latency constraints of the FIR filter, thus enabling the use of parallelism or pipelining to reduce the filter’s power. To complete the rest of the baseband system, we are also exploring a sign-sign LMS based carrier recovery that re-uses one of the DFE comparators for minimal overhead, as well as a mixed-signal baseband phase shifting/power combining technique for phased arrays.
Figure 1: Hybrid Decision Feedback Equalizer (DFE)
- C. Marcu, D. Chowdhury, C. Thakkar, L.-K. Kong, M. Tabesh, J. D. Park, Y. Wang, A. Afshar, A. Gupta, A. Arbabian, S. Gambini, R. Zamani, A. M. Niknejad, E. Alon, “A 90nm CMOS Low-Power 60GHz Transceiver with Integrated Baseband Circuitry,” IEEE International Solid State Circuits Conference, Feb 2009.