Electrical Engineering
      and Computer Sciences

Electrical Engineering and Computer Sciences


UC Berkeley


2010 Research Summary

Yield-constrained digital circuit design

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Yu Ben, Laurent El Ghaoui, Kameshwar Poolla and Costas J. Spanos


Circuit design under process variation can be formulated mathematically as a robust optimization problem with a yield constraint [1]. Existing methods force designers to either resort to overly simplified circuit performance model, or rely on simplistic variability assumptions. On the other hand, accurate yield estimation must incorporate a sophisticated variability model that recognizes both systematic and random components at various levels of hierarchy. Unfortunately, such models are not compatible with existing optimization solutions. To solve the problem, we propose the sequential geometric programming method, which consists of iterative usage of geometric programming [2] and importance sampling [3]. High efficiency of both geometric programming and importance sampling enables the method to efficiently solve circuits with thousands of gates. The fact that the yield constraint is handled by simulation makes the approach applicable to any variability model. The proposed method is applied to 8-bit adder and also ISCAS’85 benchmark circuit families. They are shown to be able to achieve the desired yield without overdesign. We are currently extending the methodology to the design of SRAM cells.

Figure 1
Figure 1: Worst-case design vs. yield-constrained design

M. Mani and M. Orshansky, “A new statistical optimization algorithm for gate sizing,” IEEE International Conference on Computer Design (2004)
S. P. Boyd, S.-J. Kim, D. D. Patil, and M. A. Horowitz, “Digital circuit optimization via geometric programming,” Oper. Res., vol. 53, no. 6, pp. 899–932 (2005)
L. Dolecek, M. Qazi, D. Sha and A. Chandrakasan, “Breaking the simulation barrier: SRAM evaluation through norm minimization,” ICCAD (2008)