Electrical Engineering and Computer Sciences

Electrical Engineering and Computer Sciences

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UC Berkeley

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2010 Research Summary

Impact of Line Edge Roughness on Tri-Gate Bulk MOSFET Performance

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Xin Sun, Tsu-Jae King Liu and Nattapol Damrongplasit

Integrated Modeling Process and Computation for Technology (IMPACT)

The effect of Gate Line-Edge Roughness on the performance of Planar and Tri-Gate Bulk MOSFET structures has been studied via 3-D device simulation. The result shows that Tri-Gate Bulk MOSFET structure shows less gate-LER-induced variation in performance.