Electrical Engineering
      and Computer Sciences

Electrical Engineering and Computer Sciences

COLLEGE OF ENGINEERING

UC Berkeley

   

2010 Research Summary

Maven (Malleable Array of Vector-thread ENgines)

View Current Project Information

Christopher Batten1, Yunsup Lee, Rimas Avizienis, Christopher Celio, Alex Bishara2, Richard Xia3 and Krste Asanović

In earlier work at MIT, Professor Asanovic's team developed the Scale vector-thread architecture and processor prototype, which combines data-level and thread-level parallel execution models in a single unified architecture. Maven is the second-generation vector-thread architecture, designed to scale up to hundreds of execution lanes, and with the goal of providing very high throughput at low energy for a wide variety of parallel applications. Maven is based on a new compact lane design, which is replicated to yield a "sea of lanes" execution substrate. At run-time, lanes are ganged together to form variable-sized vector-thread engines, sized to match application needs.

1MIT
2UCB
3UCB