Electrical Engineering
      and Computer Sciences

Electrical Engineering and Computer Sciences

COLLEGE OF ENGINEERING

UC Berkeley

   

2010 Research Summary

Integrated Circuit Variability Modeling and Statistical Parameter Extraction

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Kun Qian and Costas J. Spanos

Spatial variation plays a key role in the performance of modern ICs. Hence, we proposed a hierarchical process variability model [1-2]. Used in conjunction with 90nm and 45nm test including ring oscillator frequency and leakage measurement, the systematic chip-to-chip and within-chip variations are sufficiently described by deterministic spatial functions across-wafer and across-die. The residuals of these functions are shown to be identically, independently, normally distributed (IIND), rendering the concept of “spatial correlation” unnecessary. Our current effort is to integrate this hierarchical spatial variability modeling methodology into the compact modeling extraction flow. As the comparison between experimental data and SPICE simulation shows (Figure 2), a conventionally calibrated SPICE model can fit the electrical performance corners very well, however it cannot capture the large across-wafer systematic variations in conjuncture with real process data. This is due to the standard model extraction procedure, which is based on small set of nominal dies and devices. Our proposed method is to introduce the hierarchical structure in to existing compact models like BSIM or PSP, and extract the statistical moments and spatial characteristics simultaneously over a number of samples within the chip and across the wafer (Figure 3). A parameter extractor capable of optimizing model parameters for multiple transistors with spatial variation constraints is under development. Test circuits will be designed for model verification and in order to study the correlation between device variability and in-situ performance monitors like ring oscillator and SRAM cells.

Figure 1
Figure 1: Variability hierarchy: a) wafer-to-wafer, b) across-wafer, c) die-to-die d) Across-chip, e) layout dependent effect, f) device-to-device white noise

Figure 2
Figure 2: Existing SPICE model accurately models the median value of chip speed, but fails in capturing the large systematic across-wafer variation, given fab-measured LEFF data.

Figure 3
Figure 3: Proposed Spatial Variation Aware Model Extraction Procedure

[1]
Kun Qian, Costas J. Spanos, “A Comprehensive Model of Process Variability for Statistical Timing Optimization”, Proc. SPIE Int. Soc. Opt. Eng. 6925, 69251G (2008), DOI:10.1117/12.772980
[2]
Kun Qian, Borivoje Nikolic and Costas J. Spanos, “Hierarchical Modeling of Spatial Variability with a 45nm Example”, SPIE Advanced Lithography 2009