SRAM Yield Enhancement with Thin-BOX FD-SOI
Changhwan Shin, Min Hee Cho, Borivoje Nikolic and Tsu-Jae King Liu
SOITEC, Samsung and Korea Foundation for Advanced Studies
The performance and yield of 6-T SRAM cells implemented in thin-BOX FD-SOI technology vs. bulk technology are compared via 3-dimensional (3D) atomistic process and device simulations and analytical modeling for SRAM yield estimation. Performance is enhanced due to the elimination of channel dopants, and variation due to gate-LER and RDF are suppressed, for FD-SOI technology. For the same cell area (~0.07μm2), comparable SNM can be achieved with 30% higher write current, and SRAM yield is enhanced by >2 sigma.