Electrical Engineering
      and Computer Sciences

Electrical Engineering and Computer Sciences

COLLEGE OF ENGINEERING

UC Berkeley

   

2010 Research Summary

Fully Integrated Phased Array 60GHz Transceiver

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Cristian Marcu, Debopriyo Chowdhury, Chintan Thakkar, Lingkai Kong, Maryam Tabesh, Jungdong Park, Elad Alon, Ali Niknejad and JiaShu Chen

Various sources.

This research focuses on the design of a low power 60GHz phased-array transceiver that includes RF, LO, PLL and BB integrated into a single chip. A direct conversion prototype has been designed in a 90nm CMOS technology (Fig. 1) which operates from a 1.2V supply and has been optimized for 5-10Gb/s QPSK modulation centered at 60GHz. To achieve low power in receive mode, this design leverages co-integration and optimization of the mm-wave circuits with mixed-signal baseband circuits. This research will uncover the key design techniques and challenges in implementing an integrated, energy-efficient 60GHz phased-array transceiver including phase shifters, RF and baseband circuitry. Testing of this prototype will answer key questions about the feasibility of low-power mm-wave technology including range, channel characteristics, and optimal design of the baseband.

Figure 1
Figure 1: Die photo of the 60GHz transceiver.