Parallel Transistor Level Full-Chip Circuit Simulation
Ernest Kuh and Vincent Peng1
The goal of this continuing research project is to develop accurate and efficient parallel transistor level full-chip circuit simulation algorithms and tools. With increasing circuit design complexity, the huge size of circuit is pushing the capacity of transistor-level circuit simulation to the limit. Parallel computation has the potential to handle large-scale VLSI circuits in terms of memory and computation capacity.
We propose a novel domain decomposition approach to partition a circuit into a unified linear subdomain and many non-linear subcircuits based on the non-linearity of the device and the connectivity of the netlist. For the linear domain, we use an iterative approach to solve with parallel processing. For the non-linear subcircuits, we distribute the simulation into multiple processors and use direct matrix solver for each subcircuit. The convergence is ensured with proper domain decomposition and topological ordering. Orders of magnitude speedup over SPICE is observed for sets of large scale circuit designs. Further improvement on the scalability of the performance will be studied.