Josephson-CMOS Hybrid Memories
Daniel Wei, Heejoung Park, Xiaofan Meng, Hongfei Ye, Stephen R. Whiteley, Lizhen Zheng, Hoki Kim and Theodore Van Duzer
Army Research Office W911NF-08-1-0457
Josephson-CMOS hybrid random-access memories (RAMs) have the potential to remove the memory bottleneck faced by Josephson digital technology. We use high-density MOS memory cells and access them by high-speed superconductive devices. The operation at 4 K of standard commercial 0.25 mm and 0.18 µm CMOS has been extensively explored and an accurate model for digital applications has been established.
We have shown experimentally that the total access time for a single bit in the 64-kb memory system using 0.18 micron CMOS and Josephson current density of 2.5 kA per cm square is 0.6 ns, and this agrees with simulations. Bump-bonding was used to connect the two chips. [1,2]
During 2009, we are fabricating a more complete representation of a 64 kb memory, which includes both writing and reading of complete words, and measure the access times. We are also exploring the feasibility of embedding CMOS memory chips in a silicon wafer and fabricating the Josephson circuits on the planarized surface thereof.
Q. Liu, K. Fujiwara, X. Meng, S. R. Whiteley, T. Van Duzer, N. Yoshikawa, Y. Thakahashi, T. Hikita, and N. Kawai, “Latency and power measurements on a 64-kb hybrid Josephson-CMOS memory,” IEEE Trans. Appl. Superconduct., Vol. 17, pp.526-529, June 2007.
K. Fujiwara, Q. Liu, T. Van Duzer, X. Meng, and N. Yoshikawa, “New delay-time measurements on a 64-kb Josephson-CMOS hybrid memory with a 600 ps access time,” Accepted for publication in IEEE Trans. Appl. Superconduct., Fall 2009.