Electrical Engineering
      and Computer Sciences

Electrical Engineering and Computer Sciences


UC Berkeley


2010 Research Summary

Tri-Gate Bulk 6-T SRAM Design for Improved Robustness to process-induced variation

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Xin Sun, Changhwan Shin and Tsu-Jae King Liu

MARCO C2S2 2003-CT-888

Process variations and leakage control are significant challenges to the continued scaling of SRAM memories. Although industrial MOSFET designs have favored planar architectures historically, such designs rely on heavy channel doping to achieve good on/off current ratios. With the scaling of channel dimensions, dopant control has become less precise, and MOSFET parameters such as threshold voltage have exhibited increasing variability. In order to avoid reliance on heavy doping for channel control, new device architectures are being considered for memories. Among them, tri-gate bulk devices with a ground plane have been shown to exhibit improved short channel control with improved robustness [1]. In this work, the advantages of such a device will be explored within the context of robust SRAM design. Preliminary results suggest the tri-gate bulk SRAM will enhance read and write yields dramatically for low power applications, with significant enhancement for high performance applications as well.

X. Sun et al. (to appear).