Tradeoffs between transmit power, decoding power and decoding throughput for error correcting codes
Anant Sahai, Pulkit Grover and Harikrishna R Palaiyanur
Decoding architectures based on sparse-graphs are of interest because of their low complexity and ability to work close to the information theoretic limits. We investigate whether the two can be achieved simultaneously. In other words, we explore whether increasing the rate R of sparse-graph codes necessitates an increased decoding complexity as well. We derive a lower bound on the decoding complexity of the code sequence, given rate R and channel capacity C. We show that the decoding complexity (and hence power-consumption) diverges to infinity as the codes approaches capacity. For short-range applications, codes should operate far from capacity, leading to a trade-off between transmit and decoding power.
For broadcasting messages to multiple users, schemes based on time-divison multiplexing can outperform those based on superposition coding and other sophisticated techniques.
It is well understood that in VLSI implementations of decoders, decoding power increases with decoding throughput. Our recent results capture this with a theoretical modeling of power consumption on the interconnects. We demonstrate that there is a trade-off between transmit power, decoding power and decoding throughput for a fixed rate code.