Electrical Engineering
      and Computer Sciences

Electrical Engineering and Computer Sciences


UC Berkeley


2010 Research Summary

Source/Drain and Contact Design for High Performance and Low Standby Power Nanoscale MOSFETs

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Reinaldo Vega and Tsu-Jae King Liu

MARCO MSD and IBM/GRC Fellowship

Conventional MOSFET design for different power-performance conditions (e.g., high performance [HP] and low standby power [LSTP]) have traditionally relied upon changes in device geometry and doping parameters. For example, an LSTP device, which necessarily has lower off-state current than a HP device, may utilize a larger sidewall spacer and/or a lower source/drain extension (SDE) implant dose. For devices in the nanoscale regime, however, the optimal source/drain designs for different power-performance conditions may differ by something more fundamental than geometry and doping--the material itself.

Metallic source/drain (MSD) MOSFETs have received attention for nanoscale CMOS due to the reduced source/drain series resistance achievable with such structures. However, since the structure relies upon an aggressive silicide formation, the distance between the silicide junction and the SDE junction to the body region is small. Consequently, tunneling through the SDE region will give rise to ambipolar leakage, thereby increasing the leakage floor. Changing the SDE doping (Figure 1) and junction depth (Figure 2) can reduce this leakage, although ultimately the minimum leakage achievable is a tradeoff between SDE tunneling and band-to-band tunneling (BTBT). This constrains the LSTP design space for MSD MOSFETs such that the Ion:Ioff tradeoff is manifested in a tradeoff between tunneling leakage and contact resistance.

For HP design, the leakage specification is much higher, which permits higher SDE doping to the point where contact resistance is insignificant and source/drain series resistance dominates, thus increasing the design space for MSD MOSFETs. The focus of this work is to determine, through TCAD modeling and experimentation, whether HP and LSTP multi-gate MOSFET designs in the nanoscale regime can be optimized with a single source/drain architecture, as in the past, or whether two fundamentally different approaches are necessary. Different 3D MOSFET structures are under investigation for both their DC and AC parasitics and how these parasitics influence the optimal device design, as well as whether or not alternative materials such as silicon germanium may be incorporated in creative ways to improve performance.

Figure 1
Figure 1: NMOS leakage floor vs. source/drain extension doping concentration in a 15 nm gate length symmetric double gate MSD MOSFET, with VDS = 1 V, and varying source/drain silicides and gate underlap to the metal-semiconductor junction. The SDE length is 5 nm in all cases.

Figure 2
Figure 2: NMOS leakage floor vs. source/drain extension length (i.e., where the extension doping drops to 1x1018 cm-3) for the symmetric double gate MSD MOSFET in Figure 1 using NiSi source/drain regions and a gate underlap of 8 nm