Hardware Implementation of Lossless Compression for Direct-Write Maskless Lithography Systems
Hsin-I Liu, Avideh Zakhor and Borivoje Nikolic
Semiconductor Research Corporation Task 460.011 and Defense Advanced Research Projects Agency W911NF-04-1-0304
We investigate hardware implementation of the data path compression algorithms in maskless lithography. As the physical size of semiconductor devices becomes smaller, the traditional optical lithography techniques become impractical due to the physical constraints of the mask material. To solve this problem, direct-write maskless lithography approaches are under consideration.
To achieve acceptable throughput with maskless lithography, we have to deal with the data rates of 500 Gb/s, and as such, data compression techniques need to be applied. Specifically, the layout data is compressed beforehand, sent to the writer, and decompressed inside the writer to generate actual pixel values.
Vito Dai has developed a lossless compression scheme, called C4, for layout that outperforms all other lossless compression techniques such as LZ and its variations. In this project, we consider hardware implementation aspects of the decoder for the variations of the C4 algorithm. Our approach is to first develop the hardware block diagram model of the decoder, and then use the digital circuit design tool to make the decoder in hardware. The final goal is to combine the C4 decoder with the mix-signal processing circuitry (data buffer, digital to analog converters, and DRAM array) into a single writer chip for maskless lithography applications.
Figure 1: Functional block diagram of the lossless compression algorithm