Electrical Engineering
      and Computer Sciences

Electrical Engineering and Computer Sciences

COLLEGE OF ENGINEERING

UC Berkeley

   

2009 Research Summary

Process Independent, Fully Differential Regulated PLL for Direct Waveform Synthesis

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Nam-Seog Kim, Stanley Yuan-Shih Chen and Jan M. Rabaey

Gigascale Systems Research Center

One of the critical issues in implementing high-speed, high-resolution DACs is sampling clock jitter. When the total noise power outside as well as inside the signal band is taken into account, the DAC SNR remains almost constant regardless of the sampling jitter. However, when an analog filter follows the DAC and only the noise power inside the signal band is considered, the DAC SNR degrades as the sampling clock jitter increases and the input signal frequency becomes higher, as shown in Figure 1 [1]. Thus the sampling clock jitter is serious for the high-speed DAC.

Power supply noise on a PLL’s supply inputs appears on the output as jitter. This is the largest, though not always constant, contributor to jitter. Power supply noises are VDD noise and ground bounce. In this work, both power supply and ground are included in the regulation loop. This can be achieved by using the difference between positive and negative VCO supplies as a differential control voltage as shown in Figure 2. A much smaller decoupling capacitor is included to reduce noise not attenuated by the imperfect regulation loop and for stability of the regulation loop. For low power consumption, replica compensated linear regulators are employed. Fully differential tuning also accommodates a fully differential phase frequency detector, divider, charge pump, and loop filter which isolates those blocks from supply noise. The adaptive bandwidth scheme is also applied to achieve an under-damped loop response for stability and maximum bandwidth for minimizing phase errors under varying process, environmental condition, and loop multiplication factors.

Another challenge is the distribution of the generated on-chip clock with a small uncertainty. Static CMOS gates have poor supply-induced delay sensitivity of approximately 1%-delay/1%-VDD. To reduce jitter, a compensator circuit is added to the differential clock drivers that offsets within a 10% supply-induced delay variation.

Figure 1
Figure 1: Simulation result of SNR versus fin/fs of a 10-bit DAC with and without jitter of cosine squared distribution of a=Ts/4. Here only the noise power inside the signal band fs/2 is considered.

Figure 2
Figure 2: Fully differential supply regulated adaptive band width PLL

[1]
N. Kurosawa et al., “Sampling Clock Jitter Effects in Digital-to-Analog Converters,” Measurement, Vol. 31, 2002, pp.187-199.