Electrical Engineering
      and Computer Sciences

Electrical Engineering and Computer Sciences

COLLEGE OF ENGINEERING

UC Berkeley

   

2009 Research Summary

A Fully-Integrated 90 GHz Low-Power Phased-Array Transceiver in CMOS

View Current Project Information

Ehsan Adabi, Jungdong Park, JiaShu Chen and Ali Niknejad

Phased arrays are multiple antenna systems that can focus the signal energy into a narrow beam radiating into/from specific directions, and electronically “steer” the direction of signal transmission and reception. Beam steering capability and placing nulls at undesired directions alleviate impairments such as fading, delay spread, and co-channel interference. Also, in a multi-antenna system, automatic spatial power combining relaxes the PA design requirements which improves the power dissipation and efficiency of the transmitter.

Phased arrays have been used for high data-rate communications, imaging, and radar applications due to their ability to form electronically steerable beams. They have been limited to discrete or hybrid implementations, where off-chip antennas are connected to their associated electronics (on-chip/off-chip). This approach is suitable for high-end systems and not efficient in terms of system cost, size, and power consumption.

A monolithic phased array system in silicon that integrates all radiating antenna elements, RF and high-frequency circuitry, and baseband digital processing building blocks is highly desired due to its lower complexity, power consumption, and cost, which make it suitable for consumer electronic applications. Nanoscale CMOS demonstrated the design feasibility at mm-wave frequencies where antennas are not prohibitively large to be implemented on-chip.

The goal of this research is to design a relatively wideband single-chip mm-wave phased array system. All building blocks performing up/down conversion, signal combining/dividing, low noise/high power amplification, and radiation should be capable of handling wideband signals which require employing new techniques and architectures. On-chip antennas on silicon substrate suffer from surface-wave mode excitations as well as high conductivity of the substrate which degrades the radiation efficiency. A study of the fundamental limits for the efficiency and bandwidth of on-chip antennas will be done and post-processing techniques for enhancing the performance will be investigated. This fully integrated architecture will generate and receive arbitrary two-dimensional beam patterns at a mm-wave (90 GHz) regime.

Figure 1
Figure 1: A phased array transceiver with beam steering and spatial power combining capabilities