Electrical Engineering
      and Computer Sciences

Electrical Engineering and Computer Sciences

COLLEGE OF ENGINEERING

UC Berkeley

   

2009 Research Summary

Fully Integrated 60 GHz Transceiver

View Current Project Information

Cristian Marcu, Debopriyo Chowdhury, Chintan Thakkar, Lingkai Kong, Maryam Tabesh, Jungdong Park, Elad Alon and Ali Niknejad

This research focuses on the design of a low power 60 GHz transceiver that includes RF, LO, PLL, and BB integrated into a single chip. A direct conversion prototype has been designed in a 90 nm CMOS technology (Figure 1) which operates from a 1.2 V supply and has been optimized for 5-10 Gb/s QPSK modulation centered at 60 GHz. To achieve low power in receive mode, this design leverages co-integration and optimization of the mm-wave circuits with mixed-signal baseband circuits. This research will uncover the key design techniques and challenges in implementing an integrated, energy-efficient 60 GHz transceiver including baseband circuitry. Testing of this prototype will answer key questions about the feasibility of low-power mm-wave technology including range, channel characteristics, and optimal design of the baseband.

Figure 1
Figure 1: Block diagram of the 60 GHz transceiver