Integrated Dynamic Power Supplies for SRAMs
Kyoohyun Noh and Elad Alon
Scaling down on CMOS technology continues to benefit VLSI circuit design in terms of device speed and integration density. However, this has made it challengeable to control key parameters such as device threshold voltages due to random doping fluctuation, and inter and intra-die process variability became the bottleneck of VLSI design. This is particularly critical to SRAM design since SRAM cells typically have more aggressive design rules to meet the stringent density requirement, and modern high-performance systems necessitate larger on-die memory.
In this project, we are exploring the techniques to improve the static noise margin, and compensate for the process variability, using integrated dynamic power supplies. From this scheme, we can break the deadlock of traditional R/W margin sizing-based optimization, and minimize leakage power during standby mode. The main research focus is efficient generation of on-die supply voltages via switched capacitor dc-dc converters, considering energy efficiency and area tradeoff.
Figure 1: Potential conversion efficiency range