Electrical Engineering
      and Computer Sciences

Electrical Engineering and Computer Sciences


UC Berkeley


2009 Research Summary

Air Spacer MOSFET Technology

View Current Project Information

Jemin Park and Chenming Hu

Samsung and ERSO Chair fund

In a 20 nm-gate MOSFET with oxide spacer, 77% of the gate charge is due to the gate-to-plug/diffusion capacitances. Reducing these capacitances will be an increasingly important way to improve the device speed and switching energy/power at 20 nm and beyond. Compared to an air-spacer inverter, a conventional nitride-spacer inverter has 82% longer delay and 85% larger switching energy (power consumption). Even a pure-oxide-spacer inverter has 41% longer delay and 48% larger switching energy than the air-spacer inverter.

High density memories employ the SAC technology that requires the use of nitride spacers. This significantly raises the gate-to-plug/diffusion capacitance and increases the delay and switching energy by about 60%. A novel air-spacer SAC device can preserve the 35% area benefit of a SAC device while reducing the delay and power by over 75% to levels even better than the non-SAC conventional device. It also reduces the bit-line and word-line capacitances. The result is increased DRAM and SRAM speed, reduced power, and reduced chip size. These air spacer technologies are a promising key technology for the 20 nm generation and beyond.

Figure 1
Figure 1: MOSFETs constructed with 3D simulator. In (b) and (c) part of ILD is removed to show the outlines of SAC. Lgate = 20 nm, nitride/oxide/air spacer thickness = 12 nm. (a) Non-SAC MOSFET (oxide spacer); (b) SAC MOSFET (nitride spacer); and (c) SAC MOSFET (air spacer)

Figure 2
Figure 2: The mixed-mode simulation of inverter delay. The delay of the air-spacer is decreased by 45% and 30% compared with the nitride-spacer and oxide-spacer, respectively.

M. Togo, A. Tanabe, A. Furukawa, K. Tokunaga, and T. Hashimoto, "A Gate-Side Air-Gap Structure (GAS) to Reduce the Parasitic Capacitance in MOSFETs," Symposium on VLSI Tech. Dig., p. 38, 1996.
TSUPREM4 User Manual, Synopsys, Mountain View, CA.
SENTAURUS User Manual, Synopsys, Mountain View, CA.