Electrical Engineering
      and Computer Sciences

Electrical Engineering and Computer Sciences

COLLEGE OF ENGINEERING

UC Berkeley

   

2009 Research Summary

Partition Algorithms for Parallelizing Post-Layout Timing Optimization (PAPPTO)

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Bor-Yiing Su, Kurt Keutzer and Christopher Batten1

Post-layout timing is a time-consuming procedure for the whole synthesis flow. In order to speed up this step, the most reasonable way is to parallelize the algorithms. Usually a design is composed of millions of gates, thus we must explore data parallelism to give each microprocessor a proper amount of gates to deal with in order to fit the memory within each microprocessor. As a result, we need to partition the original design into several sub-circuits and apply timing optimization on them in parallel. However, the timing optimization algorithm fixes the timing violations along paths in the circuit. Therefore, when partitioning the circuit, we need to minimize the cuts on paths with timing violation. In this project, we are trying to explore different partition algorithms to have good circuit partitions for parallel timing optimization.

1UCB