Nanoelectronic Devices and Processes for CMOS Applications
Alexandra Ford, Johnny Ho, Yu-Lun Chueh and Ali Javey
Intel and MARCO/MSD
The goal of the nanoelectronic devices and processes project is to: (1) fabricate and characterize novel one-dimensional nanomaterials; (2) investigate the fundamental physical properties of the nanomaterials; and (3) design functional nanoelectronic devices by combining “bottom-up” nanomaterials and “top-down” CMOS.
The ability to control the size, structure, composition, and morphology of semiconductor nanowires (NWs) makes them ideal one-dimensional building blocks for potential applications in high performance nanoelectronics and large-area, flexible electronics. Uniquely, nanowires can be readily assembled on various substrates using low-temperature processing conditions, therefore, making them compatible with CMOS processing while avoiding the lattice mismatch and single-crystalline growth challenges often encountered for epitaxial, planar thin films. As a result, hybrid electronics consisting of “top-down” Si CMOS and “bottom-up” nanomaterials may be envisioned for enabling advanced functionalities. InAs nanowires have been actively explored as the channel material for high-performance transistors owing to their high electron mobility and ease of ohmic metal contact formation. However, the catalytic growth of non-epitaxial InAs nanowires has often relied on the use of Au colloids which is non-CMOS compatible.
Here, we demonstrate the successful synthesis of crystalline InAs nanowires with high yield and tunable diameters by using Ni nanoparticles as the catalyst material on amorphous SiO2 substrates (Figure 1). The nanowires show superb electrical properties with field-effect electron mobility ~6000 cm2/Vs and ION/IOFF >103 (Figure 2). The uniformity and purity of the grown InAs nanowires are further demonstrated by large-scale assembly of parallel arrays of nanowires on substrates via the contact printing process that enables high-performance “printable” transistors, capable of delivering 5-10 mA ON currents (~400 nanowires) (Figure 3). Additionally, we have developed a nanoscale electrode for the InAs NWs via Ni metallization of the NWs to minimize contact resistance.
Further investigations into surface passivation of the InAs NWs as well as improvements in high- integration need to be performed to optimize parallel-array device performance.
Figure 1: (a) Ni nanoparticles are shown to serve as an efficient catalyst for (b) high-yield growth of high-mobility InAs nanowires on amorphous SiO2 substrates. The grown nanowires can be readily printed as (c) parallel arrays on substrates and configured as high-performance transistors.
Figure 2: (a) Ids-Vgs for Vds=0.1, 0.3, and 0.5 V and (b) Mobility-Vgs (at Vds=0.1 V) for a representative single InAs NW FET. The channel length L=8.1 m and the NW diameter d=40 nm.
Figure 3: (a) Ids-Vgs for Vds=0.1, 0.3, and 0.5 V for a representative parallel-array InAs NW FET with W~200 µm (~400 NWs bridging source/drain) and L=3 µm. (b) Ids-Vds for various Vgs for the same device.