Electrical Engineering
      and Computer Sciences

Electrical Engineering and Computer Sciences


UC Berkeley


2009 Research Summary

Energy-Efficient Supply-Regulated PLLs

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John Wiley Crossley and Elad Alon

Ring-oscillator-based phase-locked loops for precision clock generation/multiplication are widely deployed in high-performance digital processors and high-speed serial communication links. In these applications, the compactness and tune-ability offered by ring oscillators outweigh the higher intrinsic spectral purity of LC oscillators. Since ring oscillators are extremely sensitive to changes in their supply voltage, and since these loops are integrated into chips with significant digital functionality, reducing the effects of supply noise on the overall performance of these PLLs while maintaining low power dissipation is one of the key considerations in such designs.

In order to reduce the supply noise seen by the VCO, these PLLs typically make use of some form of supply regulation. In fact, many of these loops use the supply voltage as the control terminal for the VCO and embed the regulator into the PLL’s forward path to buffer the high impedance charge pump output. This topology also offers a straightforward method to self-bias the PLL and maintain constant loop dynamics over process, voltage, and temperature variations. However, placing the regulator in the PLL feedback loop forces the regulator to achieve high bandwidth in order to maintain the stability of the overall PLL--significantly reducing the regulator’s achievable supply rejection at a given power consumption.

Therefore, in this project we will explore a method of improving both the supply rejection and overall efficiency of such PLLs by placing the regulator outside of the forward path of the loop. Since the regulator has been removed from the control loop, another means of controlling the oscillator must be found. While analog methods to control the VCO frequency are available, most of these have only limited range and do not readily lend themselves to self-biasing. We are therefore focusing on a digital PLL implementation, where the oscillator frequency is controlled by digitally switching capacitors into the nodes of the ring oscillator, and the loop dynamics can easily be set through calibration.

Figure 1
Figure 1: Typical ring-oscillator charge pump PLL

Figure 2
Figure 2: Proposed digital PLL