Robust Design and Optimization of Deeply Scaled SRAM
Borivoje Nikolic, Zheng Guo and Seng Oon Toh
Microelectronics Advanced Research Corporation
Continued increase in the process variability is perceived to be a major challenge to future technology scaling. These effects are most pronounced minimum-geometry devices used in SRAM cells and seriously limit the scalability of SRAM circuits beyond the 65 nm node. Recent advances in robust optimization can provide an efficient framework for optimizing memory under uncertainty. Using this framework, the design of memory will be expressed as a robust geometric program (GP).
We have been given an opportunity for a 45 nm shuttle with ST Micro. We are designing a large (~1 Mb) SRAM test-chip to investigate the effects of variations on SRAM functionality at the 45 nm and beyond. In particular, we wish to investigate and measure systematic and random variations in large SRAM arrays and correlate that with measured single device as well as single cell (test structure) variations . In addition, we also hope to use the test-chip to help us extract the parameter variations in 45 nm SRAM.
Figure 1: Die photo of the 45 nm test-chip
- Z. Guo, A. Carlson, L. T. Pang, K. Duong, T. J. King, and B. Nikolic, "Large-Scale Read/Write Margin Measurement in 45 nm CMOS SRAM Arrays," VLSI Circuits, 2008.