Electrical Engineering
      and Computer Sciences

Electrical Engineering and Computer Sciences


UC Berkeley


2009 Research Summary

Synchronization in On-Chip Sensor Networks

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Ping-Chen Huang, Simone Gambini and Jan M. Rabaey

Gigascale Systems Research Center

Clock power has become one of the greatest limitations in distributing a global clock from a central clock buffer though the chip due to increasing clock speeds and die sizes. The goal is to develop a low-power clock synchronization scheme.

One way is bio-inspired distributed synchronization. Without a centralized clocking, the timing of each node dynamically evolves under other nodes' interactions and finally achieves synchronization. Another way is to perform synchronization only when communication is needed.