Engineered High Mobility CMOS Substrates
Haiyan Jin1 and Nathan W. Cheung
UC Discovery, IMPACT
For GeOI fabrication, a large-area Ge layer can be successfully transferred on thermal SiO2/Si receptor wafers by either mechanical-cut or thermal-cut with N2 plasma surface activation.
A pseudo-MOSFET structure was employed to characterize interface trap density, interface fixed charge density, interface carriers mobility, and bulk carrier mobility of these GeOI substrates with various annealing conditions in forming gas ambient. High-temperature annealing in the vicinity of 500°C-600°C has shown the best carrier mobilities, with the interface trap density as low as 1x1010 q/cm2. The extracted bulk hole mobility of the annealed GeOI is near 500 cm2/V-s, which is higher than that of silicon (300 cm2/V-s) at the same doping concentration level.
We also demonstrated GeOI layer transfer using Ge epi wafers and demonstrate strained GeOI layer transfer. Both substrates show good electrical characteristics.
For work in progress, we will investigate the characteristic of GeOI with ALD high-K dielectric. We will fabricate FET structures to investigate processing compatibility of Ge devices with CMOS technology.
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