Electrical Engineering
      and Computer Sciences

Electrical Engineering and Computer Sciences

COLLEGE OF ENGINEERING

UC Berkeley

   

2009 Research Summary

Integrated Voltage Conversion for High-Performance Digital ICs

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Hanh-Phuc Le, Elad Alon and Seth R. Sanders

CMOS chips have evolved to operate at steadily lower supply voltages and increasing power densities, leading to drastic reductions in the required impedance of the supply distribution network. For example, today’s 1 V, 100 A microprocessors require a supply impedance of ~1 mΩ, which is extremely challenging to achieve across a broad range of frequencies. Indeed, this impedance requirement limits the amount of current that can be efficiently delivered onto the die, limiting the ability to improve performance by integrating additional cores. Furthermore, supporting multiple independent supply voltages on the die (for improved power management) is currently very challenging due to the impedance degradation associated with heavily partitioned package power planes.

To allow for multiple on-chip supply voltages and simplify the board- and package-level power delivery networks, in this project we are exploring a power delivery architecture consisting of many distributed, fully-integrated switching regulators (for efficient conversion of a single external high-voltage supply) combined with parallel linear regulators to control the AC impedance. Since the parallel linear regulator can be designed to spend minimal power in setting the effective supply impedance, the switching regulator can be optimized purely for conversion efficiency, maximizing the overall efficiency of the system.

The principal challenge to this approach is the achievable efficiency of the integrated converters. Due to the high Q and density of on-die capacitors, we are focusing on switched capacitor converter topologies to achieve analytically predicted efficiencies of nearly 80% at the required power density of >1 W/mm2 with standard CMOS technologies. We have a schedule to tape out a preliminary design in December 2008 in a 32 nm test chip in collaboration with AMD.

Figure 1
Figure 1: Example on-die switching converter and its peak optimal efficiency vs. power density