Double-Gate MOSFET Modeling: Asymmetric DG (BSIM)
Darsen Duane Lu, Chung-Hsun Lin, Mohan Vamsi Dunga, Tianjiao Zhang, Chenming Hu and Ali Niknejad
Semiconductor Research Corporation 1451.001
The independent double-gate field-effect transistors (IDG-FETs) (Figure 1) allow the tuning of threshold voltage by changing the back-gate voltage. This provides circuit designers with additional flexibility to resolve the tradeoff between circuit speed and power consumption. However, existing compact models (or SPICE models) do not address independent gates. The goal of this project is to develop a compact model for IDG-FETs.
We have developed the core I-V and C-V model for IDG-FET and are verifying it with TCAD simulations . Real device effects such as length-dependent back-gate factor and back-gate misalignment effects have been incorporated into the model. It is successfully implemented in the Verilog-A language and can be used in most commercial circuit simulators.
The model will be verified with measurement data when they are available.
Figure 1: (a) Bulk FinFET with two independent gates; (b) SOI FinFET with independent gates; (c) Back-gated SOI MOSFET
- D. D. Lu, M. V. Dunga, C.-H. Lin, A. M. Niknejad, and C. Hu, "A Multi-Gate MOSFET Compact Model Featuring Independent-Gate Operation," IEDM, 2007.