Fundamental Limits in Data-Retention for Standby SRAM--Experimental Results (pJoules)
Kannan Ramchandran, Jan M. Rabaey, Animesh Kumar and Huifang Qin
Gigascale Systems Research Center
With technology scaling, increasing leakage power is an issue in SRAM cache which typically occupies a significant portion of the chip area. This work explores the fundamental limits on leakage power subject to reliable data-retention in standby SRAM. Each SRAM cell has a minimum threshold voltage called DRV, for reliable data retention. This DRV parameter exhibits intra-die (and inter-die) variations in the deep submicron region. Traditional worst-case methods suggest the largest DRV (say DRV0) of a chip as the minimum supply voltage for successful data-retention.
In contrast, this work proposes aggressive reduction of retention supply voltage below DRV0, with the use of error-control coding to correct ensuing errors. Reducing supply voltage increases the failure rate, but reduces the leakage-power. This phenomenon is analyzed by deriving an optimum tradeoff between the leakage power and the retention-voltage dependent failure rate of SRAM cells. The optimum power per useful bit as a function of supply-voltage is derived, using information theoretic methods. It is observed that power per bit can be optimized over the choice of supply voltage. Hence, it is shown that about 23-52% optimum leakage power reduction can be achieved (with respect to worst-case method) for different SRAM chips in the 90 nm CMOS-technology. A Hamming code implementation with block-length 31 was proposed to prove our analytical results. The implementation achieves 12-46% power reduction, while including the cost of encoding-decoding, which is remarkably close to the theoretical optimum. The analytical results are verified by experiments using twenty-four test-chips [1,2] (see Figure 1).
Figure 1: Power per bit reduction (in percent) is illustrated for the optimum and the implemented Hamming scheme in twenty-four experimental chips. The optimum power reduction varies between 23-52%, while the corresponding numbers for implementation range from 12-46%.
- A. Kumar, H. Qin, P. Ishwar, J. Rabaey, and K. Ramchandran, "Fundamental Redundancy Versus Power Trade-Off in Standby SRAM," ICASSP, April 2007.
- A. Kumar, H. Qin, P. Ishwar, J. Rabaey, and K. Ramchandran, "Fundamental Bounds on Power Reduction During Data-Retention in Standby SRAM," ISCAS 2007, May 2007.