Electrical Engineering
      and Computer Sciences

Electrical Engineering and Computer Sciences

COLLEGE OF ENGINEERING

UC Berkeley

   

2009 Research Summary

A Comprehensive Model of Process Variability for Statistical Timing Optimization

View Current Project Information

Kun Qian and Costas J. Spanos

UC Discovery

Spatial variation plays a key role in the performance of modern ICs. Hence, we proposed a hierarchical process variability model [1]. Used in conjunction with 90 nm test data, this model has been shown to successfully address both local variability and variations across significant distances.

To verify our model for state-of-the-art technology nodes, we applied our model to a comprehensive 45 nm data set. The test chip was designed by L. T. Pang [2] and manufactured on state–of-the-art production lines consisting of arrays of ring-oscillators (RO), off-state transistors, and SRAMs, and allows for accurate and flexible measurements for the hierarchical components of our variability model (Figure 1).

According to our model, the systematic chip-to-chip and within-chip variations are sufficiently described by deterministic spatial functions across-wafer and across-die. The residuals of these functions are shown to be identically, independently, normally distributed (IIND), rendering the concept of “spatial correlation” unnecessary. Layout dependence can be well modeled as an additive component to the across-wafer function.

Further work will focus on extracting physical sources underlying circuit performance/power variation. The development of our variation model can lead to accurate predictions about the statistics of a large scale circuitry, given a small number of test structure measurements, and may become the basis of statistical circuit optimization [3].

Figure 1
Figure 1: Variability hierarchy: (a) wafer-to-wafer, (b) across-wafer, (c) die-to-die, (d) across-chip, (e) layout dependent effect, and (f) device-to-device white noise

Figure 2
Figure 2: Across-wafer RO frequency variation

Figure 3
Figure 3: Within-chip RO frequency variation map

[1]
K. Qian and C. J. Spanos, “A Comprehensive Model of Process Variability for Statistical Timing Optimization,” Proc. SPIE Int. Soc. Opt. Eng., Vol. 6925, No. 69251G, 2008, DOI: 10.1117/12.772980.
[2]
L.-T. Pang and B. Nikolić, “Measurement and Analysis of Variability in 45 nm Strained-Si CMOS Technology,” Custom Integrated Circuits Conference, 2008.
[3]
Q. Y. Tang, "Layout Optimization Based on a Generalized Process Variability Model," Proceedings of SPIE, 2008.