Modeling Timing Across the Lithographic Process Window
Eric Y Chin and Andrew R. Neureuther
Feature Level Compensation and Control Grant and Semiconductor Research Corporation 1443.001
This project tests top down and bottom up models for circuit delay across the lithography process window. The models currently used in EDA tools to assess timing as affected by process variations utilize evaluations at the fast-fast and slow-slow corners which often lead to overly conservative design. The goal of this work is to explore the feasibility of establishing reduced parameter compact models for predicting timing at any point in the focus-exposure process window. Such models might be the foundation for new prototype data structures for timing simulation and they potentially enable the incorporation of layout process sensitivity estimates from fast-CAD techniques such as pattern matching.
The top-down approach is to make a detailed study of the timing variation of typical circuits across the focus-dose window and determining its characteristic shape. This is carried out by selecting circuits from actual layouts, applying geometry corrections from imaging, extracting physical dimensions and their effects on resistance and capacitance, and then computing signal delay. The bottom up approach is to seek algebraic models for geometrical changes, then resistance and capacitance, then straight runs and corners, and finally overall delay versus process parameters. The assumption that the process-induced changes can be represented by linear or quadratic is used to facilitate simplification. Results of the two approaches will be compared.
Figure 1: Pattern matching defocus match