Design of Baseband Circuits for High-Speed Wireless Communications
Borivoje Nikolic and Ji-Hoon Park
Recent advances of the CMOS RF technology paved the way to commercially viable wireless communication systems working at multi-Gbps rate. The design of baseband circuits, however, still remains challenging because of its high data and sampling rate. The high sampling rate means that the system sees a large delay spread, which is hard to synchronize and demodulate. On the other hand, because the circuit power consumption is proportional to the data rate, reducing the power consumption of these systems is a major issue, especially for a portable system.
The purpose of my research is to develop circuits and algorithms for the wireless transceiver combating against above challenges. Specifically, I’ve been working on high-speed, power-efficient carrier/timing recovery and equalization. The research includes evaluation and development of algorithms and architectures, a proper partition between analog and digital circuits, and the circuit implementation of those blocks.